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8-bit, 125 msps, dual txdac+ digital-to-analog converter ad9709 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2000C2009 analog devices, inc. all rights reserved. features 8-bit dual transmit digital-to-analog converter (dac) 125 msps update rate excellent sfdr to nyquist @ 5 mhz output: 66 dbc excellent gain and offset matching: 0.1% fully independent or single-resistor gain control dual port or interleaved data on-chip 1.2 v reference single 5 v or 3.3 v supply operation power dissipation: 380 mw @ 5 v power-down mode: 50 mw @ 5 v 48-lead lqfp applications communications base stations digital synthesis quadrature modulation 3d ultrasound functional block diagram 1 latch 1 dac bias generator sleep digital interface ad9709 port1 port2 w rt1/iqwrt wrt2/iqsel clk2/iq reset mode 2 dac 2 latch i outb2 i outa2 i outb1 i outa1 clk1 dcom1/ dcom2 dvdd1/ dvdd2 avdd acom gainctrl fsadj2 fsadj1 refio reference 0 0606-001 figure 1. general description the ad9709 1 is a dual-port, high speed, 2-channel, 8-bit cmos dac. it integrates two high quality 8-bit txdac+? cores, a voltage reference, and digital interface circuitry into a small 48-lead lqfp package. the ad9709 offers exceptional ac and dc performance while supporting update rates of up to 125 msps. the ad9709 has been optimized for processing i and q data in communications applications. the digital interface consists of two double-buffered latches as well as control logic. separate write inputs allow data to be written to the two dac ports independent of one another. separate clocks control the update rate of the dacs. a mode control pin allows the ad9709 to interface to two separate data ports, or to a single interleaved high speed data port. in inter- leaving mode, the input data stream is demuxed into its original i and q data and then latched. the i and q data is then converted by the two dacs and updated at half the input data rate. the gainctrl pin allows two modes for setting the full-scale current (i outfs ) of the two dacs. i outfs for each dac can be set independently using two external resistors, or i outfs for both dacs can be set by using a single external resistor. see the gain control mode section for important date code information on this feature. the dacs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. each dac provides differential current output, thus supporting single- ended or differential applications. both dacs can be simultaneously updated and provide a nominal full-scale current of 20 ma. the full-scale currents between each dac are matched to within 0.1%. 1 patent pending. the ad9709 is manufactured on an advanced low-cost cmos process. it operates from a single supply of 3.3 v or 5 v and consumes 380 mw of power. product highlights 1. the ad9709 is a member of a pin-compatible family of dual txdacs providing 8-, 10-, 12-, and 14-bit resolution. 2. dual 8-bit, 125 msps dacs. a pair of high performance dacs optimized for low distortion performance provide for flexible transmission of i and q information. 3. matching. gain matching is typically 0.1% of full scale, and offset error is better than 0.02%. 4. low power. complete cmos dual dac function operates at 380 mw from a 3.3 v or 5 v single supply. the dac full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. 5. on-chip voltage reference. the ad9709 includes a 1.20 v temperature-compensated band gap voltage reference. 6. dual 8-bit inputs. the ad9709 features a flexible dual- port interface, allowing dual or interleaved input data.
ad9709 rev. b | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? dynamic specifications ............................................................... 4 ? digital specifications ................................................................... 5 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 11 ? theory of operation ...................................................................... 12 ? functional description .............................................................. 12 ? reference operation .................................................................. 13 ? gain control mode .................................................................... 13 ? setting the full-scale current ................................................... 13 ? dac transfer function ............................................................. 14 ? analog outputs .......................................................................... 14 ? digital inputs .............................................................................. 15 ? dac timing ................................................................................ 15 ? sleep mode operation ............................................................... 18 ? power dissipation....................................................................... 18 ? applying the ad9709 .................................................................... 19 ? output configurations .............................................................. 19 ? differential coupling using a transformer ............................ 19 ? differential coupling using an op amp ................................ 19 ? single-ended, unbuffered voltage output ............................. 20 ? single-ended, buffered voltage output configuration ........ 20 ? power and grounding considerations .................................... 20 ? applications information .............................................................. 22 ? quadrature amplitude modulation (qam) using the ad9709 ........................................................................................ 22 ? cdma ......................................................................................... 23 ? evaluation board ............................................................................ 24 ? general description ................................................................... 24 ? schematics ................................................................................... 24 ? evaluation board layout ........................................................... 30 ? outline dimensions ....................................................................... 32 ? ordering guide .......................................................................... 32 ? revision history 9/09rev. a to rev. b changes to power and grounding considerations section ..... 20 changes to schematics section ..................................................... 24 changes to evaluation board layout section ............................. 30 1/08rev. 0 to rev. a updated format .................................................................. universal changed single supply operation to 5 v or 3.3 v ........ universal changes to figure 1 .......................................................................... 1 added timing diagram section .................................................... 5 changes to figure 3 and table 6 ..................................................... 7 change to figure 12 ......................................................................... 9 changes to figure 18 to figure 20 ................................................ 10 changes to functional description section ............................... 13 changes to reference operation section .................................... 13 changes to figure 23 and figure 24 ............................................. 13 changes to gain control mode section ...................................... 13 replaced reference control amplifier section with setting the full-scale current section ...................................................... 13 changes to dac transfer function section............................... 14 changes to interleaved mode timing section ........................... 16 added figure 28 ............................................................................. 16 changes to power and grounding considerations section ..... 20 changes to figure 44 ...................................................................... 22 deleted figure 43 ............................................................................ 17 changes to cdma section ........................................................... 23 changes to figure 45 caption ...................................................... 23 changes to figure 46 ...................................................................... 24 changes to figure 48 ...................................................................... 26 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 5/00revision 0: initial version
ad9709 rev. b | page 3 of 32 specifications dc specifications t min to t max , avdd = 3.3 v or 5 v, dvdd1 = dvdd2 = 3.3 v or 5 v, i outfs = 20 ma, unless otherwise noted. table 1. parameter min typ max unit resolution 8 bits dc accuracy 1 integral linearity error (inl) ?0.5 0.1 +0.5 lsb differential nonlinearity (dnl) ?0.5 0.1 +0.5 lsb analog output offset error ?0.02 +0.02 % of fsr gain error without internal reference ?2 0.25 +2 % of fsr gain error with internal reference ?5 +1 +5 % of fsr gain match t a = 25c ?0.3 0.1 +0.3 % of fsr t min to t max ?1.6 +1.6 % of fsr t min to t max ?0.14 +0.14 db full-scale output current 2 2.0 20.0 ma output compliance range ?1.0 +1.25 v output resistance 100 k output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m small-signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/c gain drift without internal re ference 50 ppm of fsr/c gain drift with internal reference 100 ppm of fsr/c reference voltage drift 50 ppm/c power supply supply voltages avdd 3 5 5.5 v dvdd1, dvdd2 2.7 5 5.5 v analog supply current (i avdd ) 71 75 ma digital supply current (i dvdd ) 4 5 7 ma digital supply current (i dvdd ) 5 15 ma supply current sleep mode (i avdd ) 8 12 ma power dissipation 4 (5 v, i outfs = 20 ma) 380 410 mw power dissipation 5 (5 v, i outfs = 20 ma) 420 450 mw power dissipation 6 (5 v, i outfs = 20 ma) 450 mw power supply rejection ratio 7 avdd ?0.4 +0.4 % of fsr/v power supply rejection ratio 7 dvdd1, dvdd2 ?0.025 +0.025 % of fsr/v operating range ?40 +85 c 1 measured at i outa , driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 times the i ref current. 3 an external buffer amplifier with input bias current <100 na should be used to drive any external load. 4 measured at f clk = 25 msps and f out = 1.0 mhz. 5 measured at f clk = 100 msps and f out = 1 mhz. 6 measured as unbuffered voltage output with i outfs = 20 ma and r load = 50 at i outa and i outb , f clk = 100 msps, and f out = 40 mhz. 7 10% power supply variation.
ad9709 rev. b | page 4 of 32 dynamic specifications t min to t max , avdd = 3.3 v or 5 v, dvdd1 = dvdd2 = 3.3 v or 5 v, i outfs = 20 ma, differential transformer-coupled output, 50 doubly terminated, unless otherwise noted. table 2. parameter min typ max unit dynamic performance maximum output update rate (f clk ) 125 msps output settling time (t st ) to 0.1% 1 35 ns output propagation delay (t pd ) 1 ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (90% to 10%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/hz output noise (i outfs = 2 ma) 30 pa/hz ac linearity spurious-free dynamic range to nyquist f clk = 100 msps, f out = 1.00 mhz 0 dbfs output 63 68 dbc C6 dbfs output 62 dbc C12 dbfs output 56 dbc C18 dbfs output 50 dbc f clk = 65 msps, f out = 1.00 mhz 68 dbc f clk = 65 msps, f out = 2.51 mhz 68 dbc f clk = 65 msps, f out = 5.02 mhz 66 dbc f clk = 65 msps, f out = 14.02 mhz 60 dbc f clk = 65 msps, f out = 25 mhz 50 dbc f clk = 125 msps, f out = 25 mhz 63 dbc f clk = 125 msps, f out = 40 mhz 55 dbc signal to noise and distortion ratio f clk = 50 mhz, f out = 1 mhz 50 db total harmonic distortion f clk = 100 msps, f out = 1.00 mhz ?67 ?63 dbc f clk = 50 msps, f out = 2.00 mhz ?63 dbc f clk = 125 msps, f out = 4.00 mhz ?63 dbc f clk = 125 msps, f out = 10.00 mhz ?63 dbc multitone power ratio (eight tones at 110 khz spacing) f clk = 65 msps, f out = 2.00 mhz to 2.99 mhz 0 dbfs output 58 dbc C6 dbfs output 51 dbc C12 dbfs output 46 dbc C18 dbfs output 41 dbc channel isolation f clk = 125 msps, f out = 10 mhz 85 dbc f clk = 125 msps, f out = 40 mhz 77 dbc 1 measured single-ended into 50 load.
ad9709 rev. b | page 5 of 32 digital specifications t min to t max , avdd = 3.3 v or 5 v, dvdd1 = dvdd2 = 3.3 v or 5 v i outfs = 20 ma, unless otherwise noted. table 3. parameter min typ max unit digital inputs logic 1 voltage @ dvdd1 = dvdd2 = 5 v 3.5 5 v logic 1 voltage @ dvdd1 = dvdd2 = 3.3 v 2.1 3 v logic 0 voltage @ dvdd1 = dvdd2 = 5 v 0 1.3 v logic 0 voltage @ dvdd1 = dvdd2 = 3.3 v 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulse width (t lpw , t cpw ) 3.5 ns timing diagram see table 3 and the dac timing section for more information about the timing specifications. data in (wrt2) (wrt1/iqwrt) (clk2) (clk1/iqclk) t pd i outa or i outb 00606-002 t s t h t lpw t cpw figure 2. timing for du al and interl eaved modes
ad9709 rev. b | page 6 of 32 absolute maximum ratings table 4. thermal resistance parameter with respect to rating avdd acom ?0.3 v to +6.5 v dvdd1, dvdd2 dcom1/dcom2 ?0.3 v to +6.5 v acom dcom1/dcom2 ?0.3 v to +0.3 v avdd dvdd1/dvdd2 ?6.5 v to +6.5 v mode, clk1/iqclk, clk2/iqreset, wrt1/iqwrt, wrt2/iqsel dcom1/dcom2 ?0.3 v to dvdd1/ dvdd2 + 0.3 v digital inputs dcom1/dcom2 ?0.3 v to dvdd1/ dvdd2 + 0.3 v i outa1 /i outa2 , i outb1 /i outb2 acom ?1.0 v to avdd + 0.3 v refio, fsadj1, fsadj2 acom ?0.3 v to avdd + 0.3 v gainctrl, sleep acom ?0.3 v to avdd + 0.3 v junction temperature 150c storage temperature range ?65c to +150c lead temperature (10 sec) 300c ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja unit 48-lead lqfp 91 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad9709 rev. b | page 7 of 32 pin configuration and fu nction descriptions 48 mode 47 avdd 46 i outa1 45 i outb1 44 fsadj1 43 refio 42 gainctrl 41 fsadj2 40 i outb2 39 i outa2 38 acom 37 sleep 35 nc nc nc nc nc 34 db0p2 (lsb) 33 db1p2 30 db4p2 31 db3p2 32 db2p2 36 nc 29 db5p2 28 27 25 26 2 3 4 7 db5p1 6 db6p1 db7p1 (msb) 5 1 8 db4p1 9 db3p1 10 db2p1 12 db0p1 11 db1p1 nc = no connect 13 nc 14 nc 15 dcom1 16 dvdd1 17 wrt1/iqwrt 18 clk1/iqclk 19 clk2/iqreset 20 wrt2/iqsel 21 dcom2 22 dvdd2 23 db7p2 (msb) 24 db6p2 ad9709 top view (not to scale) 0 0606-003 nc nc nc nc pin 1 indicator figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 to 8 db7p1 to db0p1 data bit pins (port 1) 9 to 14, 31 to 36 nc no connection 15, 21 dcom1, dcom2 digital common 16, 22 dvdd1, dvdd2 digital supply voltage 17 wrt1/iqwrt input write signal for port 1 (iqwrt in interleaving mode) 18 clk1/iqclk clock input for dac1 (iqclk in interleaving mode) 19 clk2/iqreset clock input for dac2 (iqreset in interleaving mode) 20 wrt2/iqsel input write signal for port 2 (iqsel in interleaving mode) 23 to 30 db7p2 to db0p2 data bit pins (port 2) 37 sleep power-down control input 38 acom analog common 39, 40 i outa2 , i outb2 port 2 differential dac current outputs 41 fsadj2 full-scale current output adjust for dac2 42 gainctrl master/slave resistor control mode. 43 refio reference input/output 44 fsadj1 full-scale current output adjust for dac1 45, 46 i outb1 , i outa1 port 1 differential dac current outputs 47 avdd analog supply voltage 48 mode mode select (1 = dual port, 0 = interleaved)
ad9709 rev. b | page 8 of 32 typical performance characteristics avdd = 3.3 v or 5 v, dvdd = 3.3 v, i outfs = 20 ma, 50 doubly terminated load, differential output, t a = 25c, sfdr up to nyquist, unless otherwise noted. 75 70 65 60 55 50 45 0.1 1 10 100 sfdr (dbc) f out (mhz) f clk = 5msps f clk = 25msps f clk = 65msps f clk = 125msps 00606-005 figure 4. sfdr vs. f out @ 0 dbfs 75 70 65 60 55 50 45 0 0.5 1.0 1.5 2.0 2.5 sfdr (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs 00606-006 figure 5. sfdr vs. f out @ 5 msps 75 70 65 60 55 50 45 024681012 sfdr (dbc) f out (mhz) 0dbfs ?6dbfs ?12dbfs 00606-007 figure 6. sfdr vs. f out @ 25 msps 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 sfdr (dbc) f out (mhz) ?12dbfs 0dbfs ?6dbfs 00606-008 figure 7. sfdr vs. f out @ 65 msps 75 70 65 60 55 50 45 0 10203040506070 sfdr (dbc) f out (mhz) ?12dbfs 0dbfs ?6dbfs 00606-009 figure 8. sfdr vs. f out @ 125 msps 75 70 65 60 55 50 45 0 5 10 15 20 25 30 35 sfdr (dbc) f out (mhz) i outfs = 5ma i outfs = 10ma i outfs = 20ma 00606-010 figure 9. sfdr vs. f out and i outfs @ 65 msps and 0 dbfs
ad9709 rev. b | page 9 of 32 75 70 65 60 55 50 40 45 ?25 ?22 ?19 ?16 ?13 ?10 ?7 ?4 ?1 2 sfdr (dbc) 125msps/11.37mhz 65msps/5.91mhz 25msps/2.27mhz 5msps/0.46mhz 10msps/0.91mhz a out (dbfs) 00606-011 figure 10. single-tone sfdr vs. a out @ f out = f clk /11 75 70 65 60 55 50 40 45 ?25 ?20 ?15 ?10 ?5 0 sfdr (dbc) 125msps/5.0mhz 65msps/13.0mhz 25msps/5.0mhz 5msps/1.0mhz 10msps/2.0mhz a out (dbfs) 00606-012 figure 11. single-tone sfdr vs. a out @ f out = f clk /5 75 70 65 60 55 50 40 45 ?25 ?20 ?15 ?10 ?5 0 sfdr (dbc) 0.965mhz/1.035mhz @ 7msps 8.8mhz/9.8mhz @ 65msps a out (dbfs) 16.9mhz/19.1mhz @ 125msps 00606-013 3.3mhz/3.4mhz @ 25msps figure 12. dual-tone sfdr vs. a out @ f out = f clk /7 70 65 60 55 50 40 45 0 20 40 60 80 100 120 140 sinad (dbc) i outfs = 5ma i outfs = 20ma i outfs = 10ma f clk (msps) 00606-014 figure 13. sinad vs. f clk and i outfs @ f out = 5 mhz and 0 dbfs code 0.06 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0 32 64 96 160 224 128 192 256 inl (lsbs) 00606-015 figure 14. typical inl 0.07 0.05 0.03 0.01 ?0.01 0.06 0.04 0.02 0 0 50 100 150 200 250 dnl (lsbs) code 00606-016 figure 15. typical dnl
ad9709 rev. b | page 10 of 32 75 70 45 50 55 60 65 ?50 ?30 ?10 10 30 50 70 90 sfdr (dbc) temperature (c) 00606-017 f out = 10mhz f out = 25mhz f out = 40mhz f out = 60mhz figure 16. sfdr vs. temperature @ f clk = 125 msps, 0 dbfs 0.05 ?0.05 ?0.03 0 0.03 1.0 ?1.0 ?0.5 0 0.5 ?40 ?20 0 20 40 60 80 offset error (%fs) gain error (%fs) temperature (c) 0 0606-018 gain error offset error figure 17. gain and offset error vs. temperature @ f clk = 125 msps 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 06 50 40 30 20 10 sfdr (dbm) frequency (mhz) 0 0 0606-019 figure 18. single-tone sfdr @ f clk = 125 msps 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 06 50 40 30 20 10 sfdr (dbm) frequency (mhz) 0 0 0606-020 figure 19. dual-tone sfdr @ f clk = 125 msps 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 06 50 40 30 20 10 sfdr (dbm) frequency (mhz) 0 00606-021 figure 20. four-tone sfdr @ f clk = 125 msps
ad9709 rev. b | page 11 of 32 terminology linearity error (integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full-scale. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error offset error is the deviation of the output current from the ideal of zero. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error gain error is the difference between the actual and ideal output spans. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the output compliance range is the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in part per million (ppm) of full-scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius (pm/c). power supply rejection (psr) psr is the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in picovolts per second (pv-s). spurious-free dynamic range the difference, in decibels (db), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db).
ad9709 rev. b | page 12 of 32 theory of operation 5 v clk1/iqclk clk2/iqreset avdd fsadj1 refio fsadj2 1.2v ref channel 1 latch channel 2 latch mode dvdd1/ dvdd2 multiplexing logic 5v gainctrl dcom1/ dcom2 sleep acom dvdd1/dvdd2 dcom1/dcom2 ad9709 r set 1 2k? 0.1f r set 2 2k? clk divider dac1 latch pmos current source array pmos current source array wrt1/ iqwrt retimed clock output* lecroy 9210 pulse generator 50 ? digital data tektronix awg2021 with option 4 wrt2/ iqsel *awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. port 1 port 2 i outa1 i outb1 i outa2 i outb2 dac2 latch lsb switch segmented switches for dac2 segmented switches for dac1 lsb switch to hp3589a or equivalent spectrum/ network analyzer mini-circuits t1-1t 50? 50 ? 00606-004 figure 21. basic ac characterization test setup for ad9709, test ing port 1 in dual port mode, using independent gainctrl resist ors on fsadj1 and fsadj2 0.1f 5 v clk1/iqclk clk2/iqreset avdd fsadj1 refio fsadj2 1.2v ref channel 1 latch channel 2 latch mode dvdd1/ dvdd2 multiplexing logic 5v gainctrl dcom1/ dcom2 sleep digital data inputs ad9709 r set 1 2k ? i ref 1 r set 2 2k? i ref 2 wrt1/ iqwrt port 1 port 2 wrt2/ iqsel i outb2 i outa2 i outb1 i outa1 pmos current source array pmos current source array clk divider dac1 latch dac2 latch segmented switches for dac1 lsb switch segmented switches for dac2 lsb switch v diff = v out a ? v out b v out 1a v out 1b v out 2a v out 2b r l 1a 50? r l 1b 50 ? r l 2a 50? r l 2b 50 ? acom 0 0606-022 figure 22. simplified block diagram functional description figure 22 shows a simplified block diagram of the ad9709. the ad9709 consists of two dacs, each one with its own independent digital control logic and full-scale output current control. each dac contains a pmos current source array capable of providing up to 20 ma of full-scale current (i outfs ). the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits, or middle bits, consist of 15 equal current sources whose value is 1/16 th of an msb current source. the remaining lsb is a binary weighted fraction of the middle bit current sources. implementing the middle and lower bits with current sources instead of an r-2r ladder enhances the dynamic performance for multitone or low amplitude signals and helps maintain the high output impedance of each dac (that is, >100 k). all of these current sources are switched to one of the two output nodes (that is, i outa or i outb ) via the pmos differential current switches. the switches are based on a new architecture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching of complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9709 have separate power supply inputs (that is, avdd and dvdd1/dvdd2) that can operate independently over a 3.3 v to 5 v range. the digital section, which is capable of operating up to a 125 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v band gap voltage reference, and two reference control amplifiers.
ad9709 rev. b | page 13 of 32 the full-scale output current of each dac is regulated by separate reference control amplifiers and can be set from 2 ma to 20 ma via an external network connected to the full-scale adjust (fsadj) pin. the external network in combination with both the reference control amplifier and voltage reference (v refio ) sets the reference current (i ref ), which is replicated to the segmented current sources with the proper scaling factor. the full-scale current (i outfs ) is 32 i ref . reference operation the ad9709 contains an internal 1.20 v band gap reference. this can easily be overridden by a low noise external reference with no effect on performance. refio serves as either an input or output depending on whether the internal or an external reference is used. to use the internal reference, simply decouple the refio pin to acom with a 0.1 f capacitor. the internal reference voltage will be present at refio. if the voltage at refio is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 na should be used. an example of the use of the internal reference is shown in figure 23 . ad9709 reference section avdd gainctrl refio fsadj1/ fsadj2 acom current source array 1.2v ref i ref 0.1f optional external reference buffer additional external load r set 256 ? 22nf 00606-023 figure 23. internal reference configuration an external reference can be applied to refio as shown in figure 24 . the external reference can provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required because the internal reference is overridden and the relatively high input impedance of refio minimizes any loading of the external reference. ad9709 reference section avdd gainctrl refio fsadj1/ fsadj2 acom avdd current source array external reference 1.2v ref 0 0606-024 i ref r set 256? 22nf figure 24. external reference configuration gain control mode the ad9709 allows the gain of each channel to be set independently by connecting one r set resistor to fsadj1 and another r set resistor to fsadj2. to add flexibility and reduce system cost, a single r set resistor can be used to set the gain of both channels simultaneously. when gainctrl is low (that is, connected to analog ground), the independent channel gain control mode using two resistors is enabled. in this mode, individual rset resistors should be connected to fsadj1 and fsadj2. when gainctrl is high (that is, connected to avdd), the master/slave channel gain control mode using one network is enabled. in this mode, a single network is connected to fsadj1, and the fsadj2 pin must be left unconnected. note that only parts with a date code of 9930 or later have the master/slave gain control function. for parts with a date code before 9930, pin 42 must be connected to agnd, and the part operates in the two-resistor, independent gain control mode. setting the full-scale current both of the dacs in the ad9709 contain a control amplifier that is used to regulate the full-scale output current (i outfs ). the control amplifier is configured as a v-i converter, as shown in figure 23 , so that its current output (i ref ) is determined by the ratio of the v refio and an external resistor, r set . set refio ref r v i = the dac full-scale current, i outfs , is an output current 32 times larger than the reference current, i ref . ref outfs i i = 32 the control amplifier allows a wide (10:1) adjustment span of i outfs from 2 ma to 20 ma by setting i ref between 62.5 a and 625 a. the wide adjustment range of i outfs provides several benefits. the first relates directly to the power dissipation of the ad9709, which is proportional to i outfs (refer to the power dissipation section). the second relates to the 20 db adjustment, which is useful for system gain control purposes. it should be noted that when the r set resistors are 2 k or less, the 22 nf capacitor and 256 resistor shown in figure 23 and figure 24 are not required and the reference current can be set by the r set resistors alone. for r set values greater than 2 k, the 22 nf capacitor and 256 resistor networks are required to ensure the stability of the reference control amplifier(s). regardless of the value of r set , however, if the r set resistor is located more than ~10 cm away from the pin, use of the 22 nf capacitor and 256 resistor is recommended.
ad9709 rev. b | page 14 of 32 dac transfer function both dacs in the ad9709 provide complementary current out- puts, i outa and i outb . i outa provides a near full-scale current output, i outfs , when all bits are high (that is, dac code = 256) while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as i outa = ( dac code/256) i outfs (1) i outb = (255 ? dac code )/256 i outfs (2) where dac code = 0 to 255 (that is, decimal representation). i outfs is a function of the reference current (i ref ), which is nominally set by a reference voltage (v refio ) and an external resistor (r set ). it can be expressed as i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be connected directly to matching resistive loads, r load , that are tied to the analog common, acom. note that r load can represent the equivalent load resistance seen by i outa or i outb , as would be the case in a doubly terminated 50 or 75 cable. the single-ended voltage output appearing at the i outa and i outb nodes is v outa = i out a r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb must not exceed the specified output compliance range to maintain the specified distortion and linearity performance. v diff = ( i outa ? i outb ) r load (7) equation 7 highlights some of the advantages of operating the ad9709 differentially. first, the differential operation helps cancel common-mode error sources associated with i outa and i outb , such as noise, distortion, and dc offsets. second, the differential code-dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (that is, v outa or v outb ), thus providing twice the signal power to the load. note that the gain drift temperature performance for a single- ended (v outa and v outb ) or differential output (v diff ) of the ad9709 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship. analog outputs the complementary current outputs, i outa and i outb , in each dac can be configured for single-ended or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in equation 5 through equation 7. the differential voltage, v diff , existing between v outa and v outb can be converted to a single-ended voltage via a transformer or differential amplifier configuration. the ac performance of the ad9709 is optimum and specified using a differential transformer-coupled output in which the voltage swing at i outa and i outb is limited to 0.5 v. if a single-ended unipolar output is desirable, i outa should be selected. the distortion and noise performance of the ad9709 can be enhanced when it is configured for differential operation. the common-mode error sources of both i outa and i outb can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. this is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (that is, assuming no source termination). because the output currents of i outa and i outb are complementary, they become additive when processed differentially. a properly selected transformer allows the ad9709 to provide the required power and voltage levels to different loads. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos switches associated with the current sources and is typically 100 k in parallel with 5 pf. it is also slightly dependent on the output voltage (that is, v outa and v outb ) due to the nature of a pmos device. as a result, maintaining i outa and/or i outb at a virtual ground via an i-v op amp configuration results in the optimum dc linearity. note that the inl/dnl specifications for the ad9709 are measured with i outa maintained at a virtual ground via an op amp. i outa and i outb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of ?1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the ad9709. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . when i outfs is decreased from 20 ma to 2 ma, the positive output compliance range degrades slightly from its nominal 1.25 v to 1.00 v. the optimum distortion performance for a single-ended or differential output is achieved when the maximu m full-scale signal at i outa and i outb does not exceed 0.5 v. applications requiring the ad9709 output (that is, v outa and/or v outb ) to extend its output compliance range should size r load accordingly. operation beyond this compliance range adversely affects the linearity performance of the ad9709 and subsequently degrade its distortion performance.
ad9709 rev. b | page 15 of 32 digital inputs the digital inputs of the ad9709 consist of two independent channels. for the dual port mode, each dac has its own dedicated 8-bit data port: wrt line and clk line. in the interleaved timing mode, the function of the digital control pins changes as described in the interleaved mode timing section. the 8-bit parallel data inputs follow straight binary coding where db7p1 and db7p2 are the most significant bits (msbs) and db0p1 and db0p2 are the least significant bits (lsbs). i outa produces a full-scale output current when all data bits are at logic 1. i outb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. the dac outputs are updated following either the rising edge or every other rising edge of the clock, depending on whether dual or interleaved mode is used. the dac outputs are designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulse width. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. dac timing the ad9709 can operate in two timing modes, dual and interleaved, which are described in the following sections. the block diagram in figure 25 represents the latch architecture in the interleaved timing mode. iqsel iqwrt dac1 interleaved data in, port 1 iqclk iqreset dac2 2 port 1 input latch port 2 input latch deinterleaved data out dac1 latch dac2 latch 00606-027 figure 25. latch structure in interleaved mode dual port mode timing when the mode pin is at logic 1, the ad9709 operates in dual port mode (refer to figure 21 ). the ad9709 functions as two distinct dacs. each dac has its own completely independent digital input and control lines. the ad9709 features a double-buffered data path. data enters the device through the channel input latches. this data is then trans- ferred to the dac latch in each signal path. after the data is loaded into the dac latch, the analog output settles to its new value. for general consideration, the wrt lines control the channel input latches, and the clk lines control the dac latches. both sets of latches are updated on the rising edge of their respective control signals. the rising edge of clk should occur before or simultaneously with the rising edge of wrt. if the rising edge of clk occurs after the rising edge of wrt, a minimum delay of 2 ns should be maintained from rising edge of wrt to rising edge of clk. timing specifications for dual port mode are given in figure 26 and figure 27 . data in w rt1/wrt2 clk1/clk2 t pd i outa or i outb t s t h t lpw t cpw 00606-025 figure 26. dual port mode timing data in w rt1/wrt2 clk1/clk2 xx d1 d2 d3 d4 i outa or i outb d1 d2 d3 d4 d5 00606-026 figure 27. dual mode timing interleaved mode timing when the mode pin is at logic 0, the ad9709 operates in interleaved mode (refer to figure 25 ). in addition, wrt1 functions as iqwrt, clk1 functions as iqclk, wrt2 functions as iqsel, and clk2 functions as iqreset. data enters the device on the rising edge of iqwrt. the logic level of iqsel steers the data to either channel latch 1 (iqsel = 1) or to channel latch 2 (iqsel = 0). for proper operation, iqsel should only change state when iqwrt and iqclk are low. when iqreset is high, iqclk is disabled. when iqreset goes low, the next rising edge on iqclk updates both dac latches with the data present at their inputs. in the interleaved mode, iqclk is divided by 2 internally. following this first rising edge, the dac latches are only updated on every other rising edge of iqclk. in this way, iqreset can be used to synchronize the routing of the data to the dacs. similar to the order of clk and wrt in dual port mode, iqclk should occur before or simultaneously with iqwrt.
ad9709 rev. b | page 16 of 32 timing specifications for interleaved mode are shown in figure 28 and figure 30 . the digital inputs are cmos compatible with logic thresholds, v threshold , set to approximately half the digital positive supply (dvddx) or v threshold = dvddx/2 (20%) data in iqsel iqwrt iqclk i outa or i outb *applies to falling edge of iqclk/iqwrt and iqsel only. 500 ps 500 ps t s t h t pd t lpw t h * 00606-056 figure 28. 5 v or 3.3 v interleaved mode timing at 5 v it is permissible to drive iqwrt and iqclk together as shown in figure 29 , but at 3.3 v the interleaved data transfer is not reliable. data in iqsel iqwrt iqclk i outa or i outb *applies to falling edge of iqclk/iqwrt and iqsel only. t h * t s t h t pd t lpw 00606-028 figure 29. 5 v only in terleaved mode timing iqsel iqwrt iqclk iqreset xx xx d1 d2 d3 d4 xx d1 d2 d3 d4 d5 interleaved data dac output port 1 dac output port 2 00606-029 figure 30. interleaved mode timing the internal digital circuitry of the ad9709 is capable of operating at a digital supply of 3.3 v or 5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd1/dvdd2 is set to accommodate the maximum high level voltage (v oh(max) ) of the ttl drivers. a dvdd1/dvdd2 of 3.3 v typically ensures proper compatibility with most ttl logic families. figure 31 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the ad9709 remains enabled if this input is left disconnected. digital input dvdd1 00606-030 figure 31. equivalent digital input because the ad9709 is capable of being clocked up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. operating the ad9709 with reduced logic swings and a corresponding digital supply (dvdd1/dvdd2) results in the lowest data feedthrough and on-chip digital noise. the drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the ad9709 as well as its required minimum and maximum input logic level thresholds.
ad9709 rev. b | page 17 of 32 digital signal paths should be kept short, and run lengths should be matched to avoid propagation delay mismatch. the insertion of a low value (that is, 20 to 100 ) resistor network between the ad9709 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. for longer board traces and high data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain clean digital inputs. the external clock driver circuitry provides the ad9709 with a low-jitter clock input meeting the minimum and maximum logic levels while providing fast edges. fast clock edges help minimize jitter manifesting itself as phase noise on a reconstructed waveform. therefore, the clock input should be driven by the fastest logic family suitable for the application. note that the clock input can also be driven via a sine wave, which is centered around the digital threshold (that is, dvddx/2) and meets the minimum and maximum logic threshold. this typically results in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. in addition, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered because it affects the effective clock duty cycle and, subsequently, cut into the required data setup and hold times. input clock and data timing relationship snr in a dac is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. the ad9709 is rising-edge triggered and therefore exhibits snr sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9709 is to make the data transition close to the falling clock edge. this becomes more important as the sample rate increases. figure 32 shows the relationship of snr to clock/data placement. 60 50 40 30 20 10 0 ?4 ?3 ?2 ?1 0 1 2 3 4 snr (dbc) time of data change relative to rising clock edge (ns) 00606-031 figure 32. snr vs. clock placement @ f out = 20 mhz and f clk = 125 msps
ad9709 rev. b | page 18 of 32 80 70 60 50 40 30 20 10 02 20 15 10 5 i avdd (ma) i outfs (ma) 00606-032 sleep mode operation the ad9709 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 3.3 v to 5 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. the sleep pin logic threshold is equal to 0.5 avdd. this digital input also contains an active pull-down circuit that ensures the ad9709 remains enabled if this input is left disconnected. the ad9709 requires less than 50 ns to power down and approximately 5 s to power back up. power dissipation the power dissipation, p d , of the ad9709 is dependent on several factors, including 5 . 5 figure 33. i avdd vs. i outfs ? the power supply voltages (avdd and dvdd1/dvdd2) 35 30 25 20 15 10 5 0 00 0.4 0.3 0.2 0.1 i dvdd (ma) ratio ( f out / f clk ) 125msps 100msps 65msps 25msps 5msps 0 0606-033 ? the full-scale current output (i outfs ) ? the update rate (f clk ) ? the reconstructed digital input waveform the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs , as shown in figure 33 , and is insensitive to f clk . conversely, i dvdd is dependent on the digital input waveform, f clk , and digital supply (dvdd1/dvdd2). figure 34 and figure 35 show i dvdd as a function of full-scale sine wave output ratios (f out /f clk ) for various update rates with dvdd1 = dvdd2 = 5 v and dvdd1 = dvdd2 = 3.3 v, respectively. note how i dvdd is reduced by more than a factor of 2 when dvdd1/dvdd2 is reduced from 5 v to 3.3 v. figure 34. i dvdd vs. ratio @ dvdd1 = dvdd2 = 5 v 18 16 14 12 10 8 6 4 2 0 00 0.4 0.3 0.2 0.1 i dvdd (ma) ratio ( f out / f clk ) . 5 125msps 100msps 65msps 25msps 5msps 0 0606-034 figure 35. i dvdd vs. ratio @ dvdd1 = dvdd2 = 3.3 v
ad9709 rev. b | page 19 of 32 applying the ad9709 output configurations the following sections illustrate some typical output configura- tions for the ad9709. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration can consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, bipolar output, signal gain, and/or level shifting, within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage results if i outa and/or i outb is connected to an appropriately sized load resistor, r load , referred to acom. this configuration may be more suitable for a single-supply system requiring a dc-coupled, ground-referred output voltage. alternatively, an amplifier can be configured as an i-v converter, thus converting i outa or i outb into a negative unipolar voltage. this configuration provides the best dc linearity because i outa or i outb is maintained at a virtual ground. note that i outa provides slightly better performance than i outb . differential coupling using a transformer an rf transformer can be used as shown in figure 36 to perform a differential-to-single-ended signal conversion. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the pass band of the transformer. an rf transformer such as the mini-circuits? t1-1t provides excellent rejection of common- mode distortion (that is, even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios can also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9709 i outa i outb mini-circuits t1-1t optional r diff 00606-035 figure 36. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (that is, v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9709. a differential resistor, r diff , can be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential coupling using an op amp an op amp can also be used as shown in figure 37 to perform a differential-to-single-ended conversion. the ad9709 is configured with two equal load resistors, r load , of 25 each. the differential voltage developed across i outa and i outb is converted to a single- ended signal via the differential op amp configuration. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion performance by preventing the dacs high- slewing output from overloading the op amps input. ad9709 500 ? 500 ? 225? 25? 25 ? ad8047 i outa i outb 225? c opt 0 0606-036 figure 37. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate from a dual supply because its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential performance of the ad9709 while meeting other syst em level objectives (that is, cost and power) should be selected. the op amps differential gain, gain setting resistor values, and full-scale output swing capabilities should be considered when optimizing this circuit. the differential circuit shown in figure 38 provides the necessary level shifting required in a single-supply system. in this case, avdd, which is the positive analog supply for both the ad9709 and the op amp, is used to level shift the differential output of the ad9709 to midsupply (that is, avdd/2). the ad8041 is a suitable op amp for this application. ad9709 500? 500? 225? 25? 25? ad8041 i outa i outb 225? c opt avdd 1k? 0 0606-037 figure 38. single-supply dc differential coupled circuit
ad9709 rev. b | page 20 of 32 single-ended, unbuffered voltage output figure 39 shows the ad9709 configured to provide a unipolar output range of approximately 0 v to 0.5 v for a doubly terminated 50 cable, because the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 . in this case, r load represents the equivalent load resistance seen by i outa or i outb . the unused output (i outa or i outb ) can be connected directly to acom or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one additional consideration in this mode is the inl (see the analog outputs section). for optimum inl performance, the single-ended, buffered voltage output configuration is suggested. ad9709 50? 25? 50 ? v outa = 0v to 0.5v i outfs = 20ma i outa i outb 00606-038 figure 39. 0 v to 0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 40 shows a buffered single-ended output configuration in which the u1 op amp performs an i-v conversion on the ad9709 output current. u1 maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output impedance effect on the inl performance of the dac, as discussed in the analog outputs section. although this single- ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by the slewing capabilities of u1. u1 provides a negative unipolar output voltage, and its full- scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs because the signal current u1 has to sink will be subsequently reduced. ad9709 i outfs = 10ma u1 i outa i outb v out = i outfs r fb c opt 200 ? r fb 200? 00606-039 figure 40. unipolar buffered voltage output power and grounding considerations power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these applications, the implementation and construction of the printed circuit board is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing as well as power supply bypassing and grounding to ensure optimum performance. figure 52 and figure 53 illustrate the recommended circuit board layout, including ground, power, and signal input/output. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. this is referred to as the power supply rejection ratio (psrr). for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dacs full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. the psrr vs. frequency of the ad9709 avdd supply over this frequency range is shown in figure 41 . 90 70 85 80 75 psrr (db) 0.20.30.40.50.60.70.80.91.01.1 frequency (mhz) 00606-040 figure 41. avdd power supply rejection ratio vs. frequency note that the data in figure 41 is given in terms of current out vs. voltage in. noise on the analog power supply has the effect of modulating the internal current sources and therefore the output current. the voltage noise on avdd, therefore, is added in a nonlinear manner to the desired i out . psrr is very code dependent, thus producing mixing effects that can modulate low frequency power supply noise to higher frequencies. worst- case psrr for either one of the differential dac outputs occurs when the full-scale current is directed toward that output. as a result, the psrr measurement in figure 41 represents a worst- case condition in which the digital inputs remain static and the full-scale output current of 20 ma is directed to the dac output being measured.
ad9709 rev. b | page 21 of 32 an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv of noise and, for simplicitys sake, all of this noise is concentrated at 250 khz (that is, ignore harmonics). to calculate how much of this undesired noise will appear as current noise superimposed on the dac full-scale current, i outfs , one must determine the psrr in decibels using figure 41 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 41 by the scaling factor 20 log(r load ). for instance, if r load is 50 , the psrr is reduced by 34 db (that is, the psrr of the dac at 250 khz, which is 85 db in figure 41 , becomes 51 db v out /v in ). proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9709 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, decouple the analog supply (avdd) to the analog common (acom) as close to the chip as physically possible. similarly, decouple dvdd1/dvdd2, the digital supply (dvdd1/dvdd2) to the digital common (dcom1/dcom2) as close to the chip as possible. for applications that require a single 5 v or 3.3 v supply for both the analog and digital supplies, a clean analog supply can be generated using the circuit shown in figure 42 . the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained by using low-esr type electrolytic and tantalum capacitors. ttl/cmos logic circuits 100f 0.1f avdd acom electrolytic tantalum ceramic 5v power supply ferrite beads 10f to 22f 00606-041 figure 42. differential lc filter for single 5 v and 3.3 v applications
ad9709 rev. b | page 22 of 32 applications information quadrature amplitude modulation (qam) using the ad9709 qam is one of the most widely used digital modulation schemes in digital communications systems. this modulation technique can be found in fdm as well as spread spectrum (that is, cdma) based systems. a qam signal is a carrier frequency that is modulated in both amplitude (that is, am modulation) and phase (that is, pm modulation). it can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. this results in an in-phase (i) carrier component and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specified carrier frequency. a common and traditional implementation of a qam modulator is shown in figure 43 . the modulation is performed in the analog domain in which two dacs are used to generate the baseband i and q components. each component is then typically applied to a nyquist filter before being applied to a quadrature mixer. the matching nyquist filters shape and limit each components spectral envelope while minimizing intersymbol interference. the dac is typically updated at the qam symbol rate, or at a multiple of the qam symbol rate if an interpolating filter precedes the dac. the use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. a quadrature mixer modulates the i and q components with the in-phase and quadrature carrier frequencies and then sums the two outputs to provide the qam signal. quadrature modulator dac 8 8 dac carrier frequency nyquist filters to mixer dsp or asic 0 90 00606-044 figure 43. typical analog qam architecture in this implementation, it is much more difficult to maintain proper gain and phase matching between the i and q channels. the circuit implementation shown in figure 44 helps improve the matching between the i and q channels, and it shows a path for upconversion using the ad8346 quadrature modulator. the ad9709 provides both i and q dacs with a common reference that will improve the gain matching and stability. r cal can be used to compensate for any mismatch in gain between the two channels. the mismatch may be attributed to the mismatch between r set1 and r set2 , the effective load resistance of each channel, and/or the voltage offset of the control amplifier in each dac. the differential voltage outputs of both dacs in the ad9709 are fed into the respective differential inputs of the ad8346 via matching networks. i out a i out b i out a i out b dcom1/ dcom2 sleep dvdd1/ dvdd2 avdd vpbf bbip bbin bbqp bbqn loip loin vout wrt1/iqwrt fsadj1 acom + spectrum analyzer ad8346 clk1/iqclk port q port i digital interface i dac wrt2/iqsel fsadj2 mode refio c filter vdiff = 1.82v p-p rl rl rb rb rb rl rl rl rl la la la la rl ca ca rb ra ra ra ad9709 rl rb ra 0 to i outfs ad8346 avdd ad976x a vdd tektronix awg2021 with option 4 i dac latch q dac latch q dac 2k ? 20k ? 0.1f notes 1. dac full-scale output current = i outfs . 2. ra, rb, and rl are thin film resistor networks with 0.1% matching, 1% accuracy available from ohmtek ornxxxxd series or equivalent. v mod v dac differential rlc filter rl = 200 ? ra = 2500 ? rb = 500 ? rp = 200 ? ca = 280pf cb = 45pf la = 10h i outfs = 11ma avdd = 5.0v vcm = 1.2v rl cb 0.1f ra cb phase splitter rohde & schwarz fsea30b or equivalent rohde & schwarz signal generator 00606-045 256 ? 22nf 2k? 20k ? 256? 22nf figure 44. baseband qam implementation using an ad9709 and ad8346
ad9709 rev. b | page 23 of 32 i and q digital data can be fed into the ad9709 in two ways. in dual port mode, the digital i information drives one input port, and the digital q information drives the other input port. if no interpolation filter precedes the dac, the symbol rate is the rate at which the system clock drives the clk and wrt pins on the ad9709. in interleaved mode, the digital input stream at port 1 contains the i and the q information in alternating digital words. using iqsel and iqreset, the ad9709 can be synchronized to the i and q data streams. the internal timing of the ad9709 routes the selected i and q data to the correct dac output. in interleaved mode, if no interpolation filter precedes the ad9709, the symbol rate is half that of the system clock driving the digital data stream and the iqwrt and iqclk pins on the ad9709. cdma code division multiple access (cdma) is an air transmit/receive scheme where the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). the effect of this is to spread the transmitted signal across a wide spectrum. similar to a discrete multitone (dmt) wave- form, a cdma waveform containing multiple subscribers can be characterized as having a high peak to average ratio (that is, crest factor), thus demanding highly linear components in the transmit signal path. the bandwidth of the spectrum is defined by the cdma standard being used, and in operation it is implemented by using a spreading code with particular characteristics. distortion in the transmit path can lead to power being transmitted out of the defined band. the ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (acp). this is a regulatory issue due to the possibility of interference with other signals being transmitted by air. regulatory bodies define a spectral mask outside of the transmit band, and the acp must fall under this mask. if distortion in the transmit path causes the acp to be above the spectral mask, filtering or different component selection is needed to meet the mask requirements. figure 45 displays the results of using the application circuit shown in figure 44 to reconstruct a wideband cdma (w-cdma) test vector using a bandwidth of 8 mhz that is centered at 2.4 ghz and sampled at 65 mhz. the if frequency at the dac output is 15.625 mhz. the adjacent channel power ratio (acpr) for the given test vector is measured at greater than 54 db. cu1 == ?80 ?120 ?70 ?90 ?110 ?50 ?60 ?100 ?40 center 2.4ghz ?130 ? 30 (db) c0 c11 frequency cu1 c0 c11 span 30mhz 3mhz 00606-046 figure 45. cdma signal, 8 mhz chip rate sampled at 65 msps, recreated at 2.4 ghz, adjacent channel power > 54 db
ad9709 rev. b | page 24 of 32 evaluation board general description the ad9709-eb is an evaluation board for the ad9709 8-bit dual dac. careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the ad9709 in any application where high resolution, high speed conversion is required. this board allows the user flexibility to operate the ad9709 in various configurations. possible output configurations include transformer coupled, resistor terminated, and single-ended and differential outputs. the digital inputs can be used in dual port or interleaved mode and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. when operating the ad9709, best performance is obtained when running the digital supply (dvdd1/dvdd2) at 3.3 v and the analog supply (avdd) at 5 v. schematics 00606-146 l1 bead bead val volt dcase val volt dcase dgnd c10 c9 dvdd avdd 2 tb1 1 tb1 blk blk blk blk red red blk blk blk blk avddin agnd l2 dvddin 3 tb1 4 tb1 r5 r2 r1 rco m r3 r4 r6 r7 r8 r9 r2 r1 rco m r3 r4 r5 r6 r7 r8 r9 r2 r1 rco m r3 r4 r5 r6 r7 r8 r9 r2 r1 rco m r3 r4 r5 r6 r7 r8 r9 22 22 22 22 1 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 rp16 rp10 rp15 rp9 inp1 inp31 inp32 inp33 inp34 inck2 inp36 inp35 inp4 inp3 inp2 inp8 inp7 inp6 inp5 inp26 inp25 inp24 inp23 inp30 inp29 inp28 inp27 inp12 inp11 inp10 inp9 inck1 inp14 inp13 figure 46. power decoupling and clocks on ad9709 evaluation board (1)
ad9709 rev. b | page 25 of 32 00606-147 out dvdd 1k u2 u2 jp2 dclkin2 dvdd cc0805 cc0805 clk clr pre q q_ j k dvdd 14 10 9 7 12 13 11 u6 sn74f112 dvdd;16 dgnd;8 .1uf c7 .01uf c8 rc0805 rc0805 rc0805 rc0805 jp16 jp5 jp4 jp3 r4 50 50 r1 jp17 50 r13 r3 50 r2 50 dvdd dvdd cc0805 cc0805 rc0603 rc0603 rc0603 t1-1tcup rc0603 1k r17 r1 8 1k r16 1k r19 c19 .1 c18 .1 rc0805 sma200up sma200up sma200up sma200up rc0603 w rt2in iqsel reset clk2in 1qclk clk1in iqwrt w rt1in sleep r6 3 50 jp13 1 2 3 4 5 6 t3 s4 dgnd;3,4,5 s3 dgnd;3,4,5 s2 dgnd;3,4,5 s1 dgnd;3,4,5 wht wht wht wht jp14 wht ds90lv048b so16 +in -in out jp9 dclkin1 1 2 15 u2 7 8 ds90lv048b so16 +in -in out out cc0805 cc0805 dvdd c34 .01uf c33 .1uf 10 a b c 1 3 clk clr pre q q_ j k 2 sw1 3 1 26 5 4 u6 15 sn74f112 a b c 2 /2 clock divider clk2 3 1 sw2 dvdd wrt1 wrt2 dvdd;16 dgnd;8 clk1 sleep jp1 dvdd rc0603 12 13 ds90lv048b en gnd vcc en ds90lv048b so16 +in -in ds90lv048b so16 +in -in val r30 dvdd 3 14 4 5 11 6 u2 16 9 so16 u2 figure 47. power decoupling and clocks on ad9709 evaluation board (2)
ad9709 rev. b | page 26 of 32 00606-148 2 2 2 2 smaedge agnd2;3,4,5 smaedge j2 agnd2;3,4,5 jp22 jp21 j1 8 3 4 9 10 13 14 2 1 5 6 15 16 11 7 12 enbl g1a g1b g2 g3 g4a g4b ibbn ibbp loin loip qbbn qbbp vout vps1 vps2 ad834 9 u3 agnd2;17 lc0805 lc0805 cc0805 cc0805 o2n o2p c24 pnd pnd c23 l6 dnp dnp l5 2 cc0603 c30 .1uf 2 cc0603 cc0603 bcase a vdd2 10v 10uf c20 .1uf c29 c27 100pf lc0805 lc0805 cc0805 cc0805 o1n o1p dnp 12c 22c dnp dnp l4 l3 dnp rc0603 rc0603 rc0603 cc0603 dnp c32 jp20 blk rc0603 etc1-1-13 sp cc0603 cc0603 rc0603 2 local osc input agnd2 tp5 50 r20 jp18 c26 100pf 100pf c25 5 4 3 1 t4 red 2 rc0603 rc0603 rc0603 rc0603 cc0603 cc0603 rc0603 modulated output avdd2 tp6 avdd2 r23 51 dnp c31 jp19 100pf c28 0 r27 r22 dnp 51 r21 r29 0 r28 1k r25 51 51 r26 dnp r24 figure 48. modulator on ad9709 evaluation board
ad9709 rev. b | page 27 of 32 00606-149 hdr040ra hdr040ra ribbon ra 9 87 65 40 4 39 38 37 36 35 34 33 32 31 30 3 29 28 27 26 25 24 23 22 21 20 2 19 18 17 16 15 14 13 12 11 10 1 p1 10 7 10 rp6 spares 10 10 10 10 10 10 10 11 6 rp6 15 2 rp5 13 4 rp5 11 6 rp5 9 8 rp5 15 2 rp6 13 4 rp6 10 9 8 rp6 10 10 10 10 10 10 10 51 2 rp6 16 1 rp5 14 3 rp5 12 5 rp5 10 7 rp5 11 6 rp6 31 4 rp6 inck1 inp1 inp3 inp2 inp4 inp5 inp6 inp7 inp8 inp9 inp10 inp11 inp12 inp13 inp14 dutp13 dclkin1 dutp14 dutp12 dutp11 dutp10 dutp9 dutp8 dutp7 dutp6 dutp5 dutp4 dutp3 dutp2 dutp1 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 r62 470 r60 470 470 r57 r54 470 470 r53 r52 470 470 r51 r33 470 470 r49 r50 470 470 r55 r56 470 r58 470 470 r59 470 r61 figure 49. digital input signaling (1)
ad9709 rev. b | page 28 of 32 00606-150 10 512 rp8 10 116 rp7 10 15 2 rp7 10 314 rp7 10 512 rp7 10 710 rp7 10 116 rp8 10 314 rp8 10 13 4 rp7 10 11 6 rp7 10 9 8 rp7 10 15 2 rp8 10 13 4 rp8 10 11 6 rp8 10 9 8 rp8 10 7 10 rp8 hdr040ra hdr040ra ribbon ra 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 5 6 7 8 9 p2 spares inp34 inp33 inp32 inp31 inp30 inp29 inp28 inp27 inp26 inp25 inp24 inp23 inp35 inp36 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 dclkin2 dutp23 dutp24 dutp33 dutp31 dutp29 dutp27 dutp25 dutp26 dutp30 dutp28 dutp32 dutp34 dutp35 dutp36 inck2 470 r4 1 r42 470 r48 470 470 r4 7 r46 470 470 r4 5 r44 470 470 r4 3 r40 470 470 r39 r38 470 r37 470 470 r36 470 r35 r34 470 figure 50. digital input signaling (2)
ad9709 rev. b | page 29 of 32 00606-151 u1 cc0805 val cc0805 cc0805 .1uf c13 c11 c12 .01uf avdd cc0805 sm a200up agnd;3,4,5 out2 s11 .1uf c14 wht refio sleep dutp27 dutp28 dutp29 dutp30 dutp31 dutp32 dutp33 dutp34 dutp35 dutp25 dutp26 dutp36 ba mode dvdd 13 2 jp8 ad9763/65/67 acom avdd clk1 clk2 db0p1 db0p2 db10p1 db10p2 db11p1 db11p2 db12p1 db12p2 db13p1msb db13p2msb db1p1 db1p2 db2p1 db2p2 db3p1 db3p2 db4p1 db4p2 db5p1 db5p2 db6p1 db6p2 db7p1 db7p2 db8p1 db8p2 db9p1 db9p2 dcom1 dcom2 dvdd1 dvdd2 fsadj1 fsadj2 ia1 ib2 ib1 ia2 mode refio acom1 sleep wrt1 wrt2 38 47 18 19 14 36 4 26 3 25 2 24 1 23 13 35 12 34 11 33 10 32 9 31 8 30 7 29 6 28 5 27 15 21 16 22 44 41 46 40 45 39 48 43 42 37 17 20 wrt2 wrt1 dutp5 dutp6 dutp7 dutp8 dutp9 dutp10 dutp11 dutp12 dutp13 dutp23 dutp1 dutp24 dutp2 dutp3 dutp4 dutp14 clk2 clk1 wht cc0805 rc0805 rc0805 sma200up agnd;3,4,5 rc07cup cc0805 rc0805 t1-1tcup 1 2 34 5 6 t5 bl1 out1 r31 10 jp23 10pf c4 val r11 o1p o1n jp6 jp7 wht s6 r6 50 50 r5 c5 10pf cc0805 rc0805 rc0805 rc07cup rc0805 cc0805 cc0805 rc0805 cc0805 rc0805 rc0805 rc0805 t1-1tcup 1 2 34 5 6 t6 10 r32 jp24 bl3 1.92k r10 bl2 r15 256 22nf c16 wht o2p 50 r8 10pf c6 10pf c15 r9 1.92k val r12 50 r7 jp10 r14 256 22nf c17 bl4 jp12 jp11 o2n wht ba val cc0805 cc0805 cc0805 acom dvdd c3 .1uf .01uf c2 c1 2 31 jp15 avdd figure 51. device under test/analog output signal conditioning
ad9709 rev. b | page 30 of 32 evaluation board layout 00606-152 figure 52. assembly, top side
ad9709 rev. b | page 31 of 32 00606-153 figure 53. assembly, bottom side
ad9709 rev. b | page 32 of 32 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 54. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model temperature range packag e description package option ad9709astz 1 C40c to +85c 48-lead low profile quad flat package [lqfp] st-48 ad9709astzrl 1 C40c to +85c 48-lead low profile quad flat package [lqfp] st-48 ad9709-ebz 1 evaluation board 1 z = rohs compliant part. ?2000C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00606-0-9/09(b)

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